As a technology which guarantees coherency of a cache that is one kind of hierarchy memories, various kinds of related technologies are known corresponding to a structure of a cache hierarchy and a structure of a system.
For example, technology related to a physical-logical address Translation Look-aside Buffer is disclosed in Japanese Patent Application Laid-Open No. 1998-283259. An information-processing unit of Japanese Patent Application Laid-Open No. 1998-283259 has a physical address array including a logical page address tag. When the content of a main memory is changed and the physical address of the changed part is notified, the information-processing unit generates a logical address from this physical address by the physical address array. Further, the information-processing unit performs invalidation processing of a level one cache based on the generated logical address.